From b952c687fa17d4eab4b59f9dbb215c1e4a644fbf Mon Sep 17 00:00:00 2001 From: Julien Grall Date: Thu, 4 Apr 2013 21:36:37 +0100 Subject: [PATCH] xen/arm: Save/Restore GICH_APR register Linux uses GICC_CTLR.EOImodeNS set to 0, which means both priority drop and deactivate interrupt functionality are made when something is written in GICC_EOIR. As the ARM manual specifies: "having an active interrupt in the List registers with a priority that is not set in the corresponding Active Priorities register" when GICV_CTLR.EOImode (ie GICC_CTLR.EOImodeNS in the guest context) result in unpredicable behavior, we need to save/restore GICH_APR. Signed-off-by: Julien Grall Acked-by: Stefano Stabellini Acked-by: Ian Campbell --- xen/arch/arm/gic.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index 49f2b203e0..3124da3c7a 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -70,6 +70,7 @@ void gic_save_state(struct vcpu *v) v->arch.gic_lr[i] = GICH[GICH_LR + i]; v->arch.lr_mask = this_cpu(lr_mask); spin_unlock_irq(&gic.lock); + v->arch.gic_apr = GICH[GICH_APR]; /* Disable until next VCPU scheduled */ GICH[GICH_HCR] = 0; isb(); @@ -87,6 +88,7 @@ void gic_restore_state(struct vcpu *v) for ( i=0; iarch.gic_lr[i]; spin_unlock_irq(&gic.lock); + GICH[GICH_APR] = v->arch.gic_apr; GICH[GICH_HCR] = GICH_HCR_EN; isb(); -- 2.30.2